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VGLeaks - Playstation 4 includes hUMA technology

C

coldfoot

Banned
hUMA collaboration example:
ifn3XnDqQapR1.gif
 
E

ElTorro

I wanted to dominate the living room. Then I took an ESRAM in the knee.
GameSeeker said:
VGleaks did a very nice job with the Durango and Orbis rumors/leaks and proved to be accurate. This new article, plus a promised follow-up, should make for good reading. Warning: it's fairly technical in nature.
Click to expand...

Nothing that's principally new in there. It was already clear from the already known feature set that the PS4 implements hUMA, however you define its details which the article itself doesn't know.
 
GameSeeker

GameSeeker

Member
Valkyr Junkie said:
Didn't AMD pretty much already confirm this last week?
Click to expand...

For whatever reason, some folks are doubting the original AMD source. So this is a second source. Also, the article has a nice example of how hUMA helps performance at the end of it. VGLeaks says they will disclose "...more information and examples of use of this architecture in a new article this week".
 
K

KidBeta

Junior Member
Just to be clear some (a fair amount) of the technical information has not been public before. But the overview kinda has been.
 
E

ElTorro

I wanted to dominate the living room. Then I took an ESRAM in the knee.
KidBeta said:
Just to be clear some (a fair amount) of the technical information has not been public before. But the overview kinda has been.
Click to expand...

Yep, it contains a more detailed description on how to use the individual memory access pathways.

By the way, this quote here

On the R10xx, the complete L2 was flushed, so any data in use by the graphics shaders (e.g. the current textures) would need to be reloaded.
Click to expand...

is, as far as I understand it correctly, something the PS4 can do but the XB1 can't. At least the other leaked documents on vgleaks state that the XB1's GPU caches have to be flushed completely.
 
R

RoboPlato

I'd be in the dick
GameSeeker said:
For whatever reason, some folks are doubting the original AMD source. So this is a second source. Also, the article has a nice example of how hUMA helps performance at the end of it. VGLeaks says they will disclose "...more information and examples of use of this architecture in a new article this week".
Click to expand...
The people that doubt AMD, the most neutral and informed party we have in tech info since they have a hand in both console development, are the people that still act like DMAs, eSRAM, and an audio chip will make up the difference between XBO and PS4.
 
E

ElTorro

I wanted to dominate the living room. Then I took an ESRAM in the knee.
velociraptor said:
So what does this mean for games?
Click to expand...

More efficient use of GPGPU for calculating stuff. This here is an example of GPGPU-accelerated fur simulation (proprietary to NVIDIA, but it's valid as a general example):

(before/after)

furz6yt5.gif


Also, the interaction between CPU/GPU is more efficient, for instance, the exchange of display lists (rendering instructions).
 
D

Deleted member 125677

Unconfirmed Member
I already knew this. Still don't know what it is
 
K

KidBeta

Junior Member
DrFurbs said:
Can someone briefly explain what this all means (hUMA tech) ?
Click to expand...

The GPU and CPU have a sort of on chip memories called a cache that is much higher bandwidth and lower latency the DRAM.

A problem can arise because they check this cache before going to the DRAM, if the CPU/GPU has a cached value that is different to the value in the other devices cache you lose coherency.

What hUMA is trying to do from what I understand is make sure that all values that require coherency have it by either snooping the other devices cache (seems to the be the case for the CPU) or by selectively invalidating a cache line (seems to be the case for the GPU).

The selectively invalidating a single cache line might not seem like a big deal, but it would seem in the past the entire GPU's L2 cache would have to flushed instead of a single line, this would mean that if you only wanted to share a small amount of data between the two coherently that you would lose the rest of the L2, this would cause pretty much every access to hit the DRAM again.
 
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