It's just a chart illustrating the dimensions of the major lithographic processes. The dimensions are measured in nanometers.
This is your standard logic cell, which incorporate a few transistors (the basic building blocks of integrated circuits):
As you can see, the cells have a height that is related to MMP (Minimum Metal Pitch) and a width that is related to CPP (Contacted Poly Pitch). These vary by process. Additionally, we need to factor in the number of tracks per cell (also vary by process) and since cell height is the number of tracks multiplied by MMP, we can compare different nodes by multiplying [MMP x CPP X Tracks] together, i.e., TSMC '16nm' would be [64nm x 90nm x 7.5T] = 43,200 and GloFo '14nm' [64nm x 78nm x 9T] = 44,928. The smaller the number, the denser the node.