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[mikezilla2]

Good digging!

So 10nm is more of a 'bridge' to 7nm according to ASML.

what will be the benifits ?

 

[E-Cat]

Any chance of someone explaining this chart to me like the idiot I am?

Thanks

It's just a chart illustrating the dimensions of the major lithographic processes. The dimensions are measured in nanometers.

This is your standard logic cell, which incorporate a few transistors (the basic building blocks of integrated circuits):

As you can see, the cells have a height that is related to MMP (Minimum Metal Pitch) and a width that is related to CPP (Contacted Poly Pitch). These vary by process. Additionally, we need to factor in the number of tracks per cell (also vary by process) and since cell height is the number of tracks multiplied by MMP, we can compare different nodes by multiplying [MMP x CPP X Tracks] together, i.e., TSMC '16nm' would be [64nm x 90nm x 7.5T] = 43,200 and GloFo '14nm' [64nm x 78nm x 9T] = 44,928. The smaller the number, the denser the node.

 

[E-Cat]

what will be the benifits ?

I don't know if it's the most useful way to look at this in terms of the perceived value of transitioning straight to 7nm over 10nm; it's simply the reality of the situation. On one axis you have to wait a year longer for the new node, but on the other hand that node is going to deliver a massive 3.3x density improvement and >65% power reduction - far greater than a standard process leap.

 

[Souldestroyer Reborn]

It's just a chart illustrating the dimensions of the major lithographic processes. The dimensions are measured in nanometers.

This is your standard logic cell, which incorporate a few transistors (the basic building blocks of integrated circuits):

As you can see, the cells have a height that is related to MMP (Minimum Metal Pitch) and a width that is related to CPP (Contacted Poly Pitch). These vary by process. Additionally, we need to factor in the number of tracks per cell (also vary by process) and since cell height is the number of tracks multiplied by MMP, we can compare different nodes by multiplying [MMP x CPP X Tracks] together, i.e., TSMC '16nm' would be [64nm x 90nm x 7.5T] = 43,200 and GloFo '14nm' [64nm x 78nm x 9T] = 44,928. The smaller the number, the denser the node.

Thanks for the explanation!

 

[E-Cat]

Thanks for the explanation!

You're welcome.

It also turns out SS/GF do offer 7.5 tracks @ 14nm. Chart updated to reflect this:

 

[Chittagong]

This might be a good place to ask something I have wondered, why are different chip manufacturing generations called 'nodes'? The word implies they have branched out of some mainline development.

 

[show me your skeleton]

so uh, what happens when we hit the physical maximum (as close to 1nm as possible i guess)?

 

[Zabojnik]

so uh, what happens when we hit the physical maximum (as close to 1nm as possible i guess)?

 

[E-Cat]

Some interesting stuff here:
http://semiengineering.com/to-7nm-and-beyond/

SE: Are we really moving to 5nm? Or will that be too expensive?

Patton: That's a tricky question because what is 5nm? Somebody could take a 7nm technology, implement it with EUV, and call that 5. Rather than talking about novel materials, you may be talking about new device structures like silicon nanowires or vertical devices. We have a number of projects going in Albany on this.

---

Patton: 20nm was a misstep in my opinion. It was improved with a 14/16nm finFET, but it was really a 20nm process. 10nm was another misstep. There is not a huge value proposition in terms of performance. With local layout effects, they're getting very little performance improvement. There is a power benefit, but very little in terms of performance or cost. If people rush to 5nm, it could be a repeat of 10. If we take our time and really define the node, then it could be a good technology node.

Yup, it definitely sounds like the next-gen consoles will be built either on GF's 7nm (2020) or 7nm+ (2021) APUs -- after which it will probably take a long time to get to "real 5nm" that will use something like stacked silicon nanowires, and who knows what will come after that? Due to the development of new nodes becoming slower and trickier, the 10th generation of consoles may be pushing 2030.

 

[Renekton]

As the average GAF reductionist, I'm gonna read that as next-generation in 2021

 

[kitsuneyo]

Great post OP, you explained to a layman really well. Seems like a pretty good deduction to me. 7nm will make some incredible devices possible, esp when you consider Switch has 20nm chips (I think).

 

[Crash331]

What's the physical limit of those? 2nm?

I've heard smaller than 4 or 5nm starts having issues with quantum tunneling. Who knows where new tech will leads us, though.

I think the physical constraints of how the wafers are made is about 1nm. After that, we need quantum computing to keep up the pace.

 

[E-Cat]

Great post OP, you explained to a layman really well. Seems like a pretty good deduction to me. 7nm will make some incredible devices possible, esp when you consider Switch has 20nm chips (I think).

It does. A 7nm Switch 2 in 2022 would probably match PS4.

I've heard smaller than 4 or 5nm starts having issues with quantum tunneling. Who knows where new tech will leads us, though.

I think the physical constraints of how the wafers are made is about 1nm. After that, we need quantum computing to keep up the pace.

Here's some recent comments from Samsung on what the ultimate limits may be:
https://semiengineering.com/samsung-unveils-scaling-packaging-roadmaps/
http://www.eetimes.com/document.asp?doc_id=1331785

The most forward-looking of Samsung's Wednesday announcements, which were unveiled at the company's annual U.S. foundry technology forum in Santa Clara, Calif., is the company's proprietary next-generation device architecture, which it calls multi-bridge channel FET (MBCFET). The structure is described as Samsung's own proprietary flavor of gate-all-around FET (GAAFET) technology that uses a nanosheet device to overcome the physical scaling and performance limitations of the FinFET architecture.

This is the first time a foundry has publicly discussed a timetable for delivering GAA FETs, but roadmaps exist within a number of companies for several more nodes. That includes EUV lithography, GAA FETs using vertical and horizontal nanowires, and nanosheet FETs.

---

Kinam Kim, president of Samsung's Semiconductor Business, said during a presentation at a recent event sponsored by Imec, a Belgium R&D organization, that the company sees a path to logic transistor scaling down to 1.5nm.

Then, using a 2D material called molybdenum disulfide (MoS2), Samsung believes it could scale logic technology even further. Samsung and others are exploring so-called MoS2 FETs. ”We believe around 1nm is possible," Kim said. Still in the R&D stage, MoS2 is a family of transition metal dichalcogenide (TMD) materials. The TMDs have remarkable electronic, optical and mechanical properties.

 

[StereoVsn]

Yup, it definitely sounds like the next-gen consoles will be built either on GF's 7nm (2020) or 7nm+ (2021) ASICs -- after which it will probably take a long time to get to "real 5nm" that will use something like stacked silicon nanowires, and who knows what will come after that? Due to the development of new nodes becoming slower and trickier, the 10th generation of consoles may be pushing 2030.

I thought GF was going to have 7nm in 2018 and full production in 2019? I think 2020 sounds a bit late.

 

[E-Cat]

I thought GF was going to have 7nm in 2018 and full production in 2019? I think 2020 sounds a bit late.

Not really, entering initial volume production in late 2018 is perfectly in line with what you would expect for a 2020 console chip, process wise.

The pecking order is:

mobile SoC --> discrete GPU --> console APU, each a year or so apart.