JonathanPower
Member
That is the fucking x86 decoder, (as in the max instructions per cycle that it can decode into micro ops) that is not the CPUs IPC when processing a load!
So what do you think this means?
The IPC of Piledriver and Jaguar CPU cores should be pretty close.
http://beyond3d.com/showpost.php?p=1667582&postcount=43
Bobcat/Jaguar core can issue up to 6 instructions per clock (it has a dual port integer scheduler, a dual port AGU scheduler and a float "coprocessor" scheduler that can issue 2 instructions per clock). It however cannot decode/retire more than 2 instructions per clock.
In comparison a BD/PD module (2 cores) can issue 2x4+4 instructions = 12 instructions per clock, and decode/retire 4 instructions. So a BD/PD module (two cores) provides exactly the same peak and sustained rates as two Bobcat/Jaguar cores.
Of course shared decode and especially shared retire are a boon for BD/PD average IPC, since the processor can temporarily boost the sustained decode/retire rate of a core when the another code stalls (pipeline bubbles, cache stalls, branch misprediction, etc). The peak (all cores running at full steam) instruction throughput of Jaguar and BD/PD cores are however exactly the same.
http://beyond3d.com/showpost.php?p=1668355&postcount=61
Yes, they are also talking about the decoder, but it's clearly part of the discussion about the IPC.