I think this is huge. I was reading the patent I posted and found this...
Someone mentioned that adding a the Processing Element (that patent I linked to) would require adding a new bus, but this patent says otherwise.
The local PE bus can have, e.g., a conventional architecture or can be implemented as a packet-switched network.
Also...
The PE is closely associated with a shared (main) memory through a high bandwidth memory connection. Although the memory preferably is a dynamic random access memory (DRAM), the memory could be implemented using other means, e.g. as a static random access memory (SRAM), a magnetic random access memory (MRAM), an optical memory, or a holographic memory, etc.
So connecting memory to this won't be a problem at all, the GDDR5 also acts as a fast enough memory, exceeding XDR in every way possible.
EDIT: TL;DR: This means BC can be achieved through this patent by ONLY NEEDING TO ADD the Processing Element(s) to the system. The GDDR5 would be able to be used for the PE.